1. Field of the Invention
The present invention relates to an ATM (Asynchronous Transfer Mode) communication apparatus, and more particularly to a device for effecting uninterrupted switching between active and backup systems on a reception side of an ATM communication apparatus.
2. Description of the Related Art
For uninterrupted switching on a transmission path between active and backup systems (also referred to as "system 0" and "system 1") of an ATM communication apparatus, ATM cells of input data from the transmission path are kept in phase with each other at all times between the active and backup systems on a reception side of the ATM communication apparatus. For performing such a function, it is necessary to hold ATM cells to be transmitted in the same sequence between the system 0 and the system 1 on a transmission side of the ATM communication apparatus.
To meet such a requirement, heretofore, the transmission side of the ATM communication apparatus has a circuit for sending a reset signal from the active system to the backup system when a format conversion buffer underflows to simultaneously initializing buffer operation, a circuit for indicating the leading position of an ATM cell with respect to the overhead of an SDH (Synchronous Digital Hierarchy) frame from the active system to the backup system for each frame, and holding ATM cells in phase with each other, and a circuit for indicating the phase of an OAM (Operation And Maintenance) cell from the active system to the backup system and vice versa, and inserting a transmission path empty cell into one of the active and backup systems when an OAM cell is present in only the other system.
FIG. 1 of the accompanying drawings shows a reception device in a conventional ATM communication apparatus.
As shown in FIG. 1, the reception device comprises a system 0, a system 1, and switching circuits 9, 18.
The system 0 comprises a write control circuit 2, a read control circuit 3, a buffer underflow detecting circuit 4, a format conversion buffer 5, an in-device empty cell insertion circuit 7, and an in-device empty cell insertion control circuit 8.
The system 1 similarly comprises a write control circuit 11, a read control circuit 12, a buffer underflow detecting circuit 13, a format conversion buffer 14, an in-device empty cell insertion circuit 16, and an in-device empty cell insertion control circuit 17.
The format conversion buffers 5, 14 effect a format conversion on the transmission path from a format in which an ATM cell is inserted in only the payload of an SDH frame to a format in which an ATM cell is inserted in both the overhead and payload of an SDH frame, thereby to absorb the difference between transmission path lengths of the systems 0, 1.
The write control circuits 2, 11 control the writing of cells S2, S13 on the transmission path into the format conversion buffers 5, 14, respectively.
The read control circuits 3, 12 control the reading of the format conversion buffers 5, 14, respectively.
The buffer underflow detecting circuits 4, 13 monitor the amount of buffering of the format conversion buffers 5, 14, respectively, with control signals S4, S5 from the write and read control circuits 2, 3 and control signals S15, S16 from the write and read control circuits 11, 12. When an underflow is detected, the buffer underflow detecting circuits 4, 13 transmit detected underflow signals S6, S17 to the in-device empty cell insertion control circuits 8, 17 in the respective systems.
When the in-device empty cell insertion control circuit 8 receives the detected underflow signal S6, the in-device empty cell insertion control circuit 8 outputs an in-device empty cell insertion instruction signal S9 to the read control circuit 3 and the in-device empty cell insertion circuit 7.
When the in-device empty cell insertion control circuit 17 receives the detected underflow signal S17, the in-device empty cell insertion control circuit 17 outputs an in-device empty cell insertion instruction signal S20 to the read control circuit 12 and the in-device empty cell insertion circuit 16.
When the read control circuits 3, 12 receive the in-device empty cell insertion instruction signals S9, S20, respectively, the read control circuits 3, 12 do not read effective cells from the format conversion buffers 5, 14, respectively.
FIG. 2 of the accompanying drawings shows a transmission device in a conventional ATM communication apparatus, and FIG. 3 of the accompanying drawings shows a construction of a SDH frame.
The system 0 comprises a format conversion buffer 21A, a cell pulse generator 22A, a cell position byte number measuring circuit 23A, and a cell pulse generation controller 24A. The system 1 similarly comprises a format conversion buffer 21B, a cell pulse generator 22B, a cell position byte number measuring circuit 23B, and a cell pulse generation controller 24B.
These circuits are employed for the purpose of completely synchronizing the operation of circuits around format conversion buffers between the system 0 and the system 1 on the transmission side to insert transmission path empty cells into effective cells at the same position.
The cell position byte number measuring circuit 23A measures from a SPOH (overhead) signal and a cell pulse how many bytes (values a, b in FIG. 3) an ATM cell is spaced apart from positions corresponding to SOH, POH in an SDH frame, and transmits the measured number of cell position bytes to the cell pulse generation controller 24B in the system 0. The cell pulse generation controller 24B calculates the next number (value b) of cell position bytes from the number (value a) of cell position bytes measured by the cell position byte number measuring circuit 23A and the SPOH indicating signal, and controls the cell pulse generator 22B so that it generates a cell pulse at a position indicated by the value b. On the other hand, the cell pulse generation controller 24A determines a cell pulse position, independent of the system 0.
Therefore, the number of cell position bytes in the system 0 is equalized with the number of cell position bytes in the system 0. In this manner, the operation to insert transmission path empty cells is completely synchronized between the systems, thus holding ATM cells to be transmitted in the same sequence.
The in-device empty cell insertion circuits 7, 16 insert in-device empty cells into output signals S7, S18 from the format conversion buffers 5, 14 in response to the in-device empty cell insertion instruction signals S9, S20, respectively.
In the above system for effecting uninterrupted switching on the transmission path between the system 0 and the system 1 of an ATM communication apparatus, the reception side of the ATM communication apparatus is required to monitor the phase of ATM cells in the system 0 and the system 1 of input data from the transmission path, count phase differences of the ATM cells, and equalize the phase differences of the ATM cells with the format conversion buffers for absorbing the difference between the transmission path lengths of the systems 0, 1 for thereby keeping the ATM cells in the systems 0, 1 in phase with each other at all times. If the detection of underflows in the format conversion buffers differs between the systems 0, 1, then an in-device empty cell is inserted into only one of the systems 0, 1, causing a cell phase shift which makes it impossible to effect uninterrupted switching on the transmission path between the system 0 and the system 1.
A signal on the transmission path may be an OAM cell in only one of the systems 0, 1. When an OAM cell is received by only one of the systems 0, 1, a cell phase shift is caused, also making it impossible to effect uninterrupted switching on the transmission path between the system 0 and the system 1.
For achieving uninterrupted switching on the transmission path between the system 0 and the system 1 on the reception side of the ATM communication apparatus, it is necessary to hold ATM cells to be transmitted in the same sequence between the system 0 and the system 1 on the transmission side of the ATM communication apparatus. To meet such a requirement, heretofore, the transmission side of the ATM communication apparatus needs to have a circuit for sending a reset signal from the active system to the backup system when a format conversion buffer underflows to simultaneously initializing buffer operation, a circuit for indicating the leading position of an ATM cell with respect to the overhead of an SDH frame from the active system to the backup system for each frame, and holding ATM cells in phase with each other, and a circuit for indicating the phase of an OAM cell from the active system to the backup system and vice versa, and inserting a transmission path empty cell into one of the active and backup systems when an OAM cell is present in only the other system. Therefore, the ATM communication apparatus is relatively large in circuit scale.